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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
May 2008
FIN224AC 22-Bit Bi-Directional Serializer/Deserializer
Features
Industry smallest 22-bit Serializer/ Deserializer pair Low power for minimum impact on battery life
Description
The FIN224AC SerDesTM is a low-power serializer/ deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. For bidirectional operation, using half duplex for multiple sources, it is possible to reach signal reduction close to 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. The differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. It is possible to use a single PLL for most applications including bidirectional operation.

- Multiple power-down modes 100nA in standby mode, 5mA typical operating conditions Highly rolled LVCMOS edge rate option to meet regulatory requirements Cable reduction: 25:4 or greater Differential signaling: --90dBm EMI when using CTL in lab conditions -Minimized shielding -Minimized EMI filter -Minimum susceptibility to external interference Up to 22 bits in either direction Voltage translation from 1.65V to 3.6V High ESD protection: > 15kV HBM Parallel I/O power supply (VDDP) range, 1.65V - 3.6V Can support Microcontroller or RGB pixel interface
FIN224AC to FIN24AC Comparison
Up to 20% power reduction Double wide CKP pulse on FIN224AC, Mode 3 Rolled edge rate for deserializer outputs on
Applications
Image sensors Small displays
- LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive
FIN224AC, for single display applications
Same voltage range Same pinout and package
Ordering Information
Order Number
FIN224ACGFX FIN224ACMLX
Operating Temperature Range
-30 to +70C -30 to +70C
Package Description
Packing Method
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), Tape and Reel JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate) 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate) Tape and Reel
All standard Fairchild Semiconductor products are RoHS compliant and many are also "GREEN" or going green. For Fairchild's' definition of "green" please visit http://www.fairchildsemi.com/company/green/rohs_green.html
SerDesTM is a trademark of Fairchild Semiconductor Corporation.
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Basic Concept
LVCMOS FIN224AC Serializer CTL 4 FIN224AC Deserializer LVCMOS
22
22
Figure 1. Conceptual Diagram
Functional Block Diagram
CKREF STROBE Register DP[21:22] PLL + CKS0+ CKS0-
0 cksint I Serializer Control Serializer + -
DSO+/DSIDSO-/DSI+
DP[1:20]
oe Register Deserializer Deserializer Control cksint + + 100 Gated Termination CKSI+ CKSI100 Termination
DP[23:24]
Register
CKP
WORD CK Generator Control Logic
S1 S2 DIRI Power Down Control Freq Control Direction Control oe
DIRO
Figure 2. Block Diagram
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Terminal Description
Terminal Name
DP[1:20] DP[21:22] DP[23:24] CKREF STROBE CKP
I/O Type
I/O I O IN IN OUT
Number of Terminals
20 2 2 1 1 1
Description of Signals
LVCMOS parallel I/O, Direction controlled by DIRI pin LVCMOS parallel unidirectional inputs LVCMOS unidirectional parallel outputs LVCMOS clock input and PLL reference LVCMOS strobe signal for latching data into the serializer LVCMOS word clock output CTL differential serial I/O data signals(1.) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)-: Negative signal of DSO(I) pair CTL differential deserializer input bit clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI-: Negative signal of CKSI pair CTL differential serializer output bit clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO-: Negative signal of CKSO pair LVCMOS mode selection terminals used to select frequency range for the reflect, CKREF LVCMOS control input used to control direction of data flow: DIRI = "1" Serializer DIRI = "0" Deserializer LVCMOS control output inversion of DIRI Power supply for parallel I/O and translation circuitry Power supply for core and serial I/O Power supply for analog PLL circuitry For ground signals (2 for BGA, 1 for MLP)
DSO+ / DSIDSO- / DSI+
DIFF-I/O
2
CKSI+ CKSI-
DIFF-IN
2
CKSO+ CKSOS1 S2 DIRI DIRO VDDP VDDS VDDA GND
DIFF-OUT
2
IN IN IN OUT Supply Supply Supply Supply
1 1 1 1 1 1 1 2
Note: 1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientation may require that traces or cables cross.
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Connection Diagrams
32 STROBE
DP[9] DP[10] DP[11] DP[12] VDDP CKP DP[13] DP[14] DP[15] DP[16]
31 CKREF 30 DIRO 29 CKSO+ 28 CKSO27 DSO+ 26 DSO25 CKSI24 CKSI+ 23 DIRI 22 S2 21 VDDS
40 DP[8]
39 DP[7]
38 DP[6]
37 DP[5]
36 DP[4]
35 DP[3] 16
34 DP[2] 17
1 2 3 4 5 6 7 8 9 10 12 13 14 15 18 19 20 11
Figure 3. Terminal Assignments for BGA (Top View)
42 MBGA Package 3.5mm x 4.5mm (.5mm Pitcth)
(Top View)
DP[17] DP[18] DP[19] DP[20] DP[21] DP[22] DP[23] DP[24] S1 VDDA
1 A DP[9] DP[11] CKP DP[13] DP[15] DP[17] DP[19] B C D E F G
2 DP[7] DP[10] DP[12] DP[14] DP[16] DP[18] DP[20]
33 DP[1]
Pin Assignments
3 DP[5] DP[6] DP[8] VDDP GND DP[21] DP[22] 4 DP[3] DP[2] DP[4] GND VDDS VDDA DP[23] 5 DP[1] STROBE CKSO+ CKSI+ S2 DP[24] 6 CKREF DIRO CKSOCKSIDIRI S1
1 A B C D E F G
2
3
4
5
6
DSO-/DSI+ DSO+/DSI-
Figure 4. Terminal Assignments for BGA (Top View)
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Control Logic Circuitry
The FIN224AC has the ability to be used as a 22-bit serializer or a 22-bit deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the pin programming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device is configured as a serializer. Changing the state on the DIRI signal reverses the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bi-directional operation, the DIRI of the master device is driven by the system and the DIRO signal of the master is used to drive the DIRI of the slave device.
Turn-Around Functionality
The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGHimpedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, and LVCMOS inputs are driven to a valid level internally. Additionally all internal circuitry is reset. The loss of CKREF state is also enabled to ensure that the PLL only powers-up if there is a valid CKREF signal. In a typical application mode, signals of the device do not change states other than between the desired frequency range and the power-down mode. This allows for system-level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a "logic 0" should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a "logic 1" should be connected to a system-level power-down or reset signal.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for 24 bits. Because of the dedicated inputs and outputs, only 22 bits of data are serialized or deserialized. DP[21:22] inputs to the serializer are transmitted to DP[23:24] outputs on the deserializer.
Table 1. Control Logic Circuitry Mode Number
0 1
S2
0 0 0 1 1 1 1
S1
0 1 1 0 0 1 1
DIRI
x 1 0 1 0 1 0 Power-Down Mode
Description
22-Bit Serializer 2MHz to 5MHz CKREF 22-Bit Deserializer 22-Bit Serializer 5MHz to 15MHz CKREF 22-Bit Deserializer 22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data) 22-Bit Deserializer
2
3
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially identically in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the STROBE signal or not. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. The exact frequency that the reference clock needs to run at depends upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology, the minimun frequency of the spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly, if the STROBE signal has significant cycle-to-cycle variation, the maximum cycleto-cycle time needs to be factored into the selection of the CKREF frequency.
Serializer Operation: MODE 1 or MODE 2, DIRI = 1, CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. When operating in serializer mode, the internal deserializer circuitry is disabled; including the serial clock, serial data input buffers, bi-directional parallel outputs, and CKP word clock. The CKP word clock is driven HIGH.
Serializer Operation: MODE 3 (S1 = S2 =1), DIRI =1. CKREF Divide by 2 Mode.
When operating in mode 3, the effective serial speed is divided by two. This mode has been implemented to accommodate cases where the reference clock frequency is high compared to the actual strobe frequency. The actual strobe frequency must be less than or equal to 50% of the CKREF frequency for this mode to work properly. This mode, in all other ways, operates the same as described in the section where CKREF does not equal STROBE.
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization can be acheived by providing a free-running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, this device enables the CKREF serialization mode. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered down and then powered back up with a "logic 0" on CKREF.
Serializer Operation: DIRI = 1, CKREF Does Not = STROBE
If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 13 times the CKREF frequency. A data bit value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same.
Deserializer Operation Mode
The operation of the deserializer is dependent on the data received on the DSI data signal pair and the CKSI clock signal pair. The following sections describe the operation of the deserializer under distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device generating the serial data and clock signals that are inputs to the deserializer. When operating in deserializer mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon power-up (S1 or S2 = 1), deserializer output data pins are driven LOW until valid data is passed through the deserializer. serial port and deserialized through use of the bit clock sent with the data.
Deserializer Operation: DIRI = 0 (Serializer Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal in frequency to the STROBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer is different because it has non-valid data bits sent between words. The duty cycle of CKP varies based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal is equal to the STROBE frequency. In modes 1 and 2, the CKP LOW time equals half of the CKREF period of the serializer. In mode 3, the CKP LOW is equal to the CKREF period. The CKP HIGH time is approximately equal to the STROBE period, minus the CKP LOW time.
Deserializer Operation: DIRI = 0 (Serializer Source: CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value equal to half VDD. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source / sink current of approximately 0.5mA at 1.8V. The outputs are active when the DIRI signal and either S1 or S2 is asserted HIGH. When the DIRI signal and either S1 or S2 is asserted LOW, the bi-directional LVCMOS I/Os is in a HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. When S1 or S2 initially transitions HIGH, the initial state of the deserializer LVCMOS outputs is zero. Unused LVCMOS input buffers must be either tied off to a valid logic LOW or a valid logic HIGH level to prevent static current draw due to a floating input. Unused LVCMOS output should be left floating. Unused bi-directional pins should be connected to GND through a high-value resistor. If a FIN224AC device is configured as an unidirectional serializer, unused data I/O can be treated as unused inputs. If the FIN224AC is hardwired as a deserializer, unused data I/O can be treated as unused outputs.
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Application Mode Diagrams
SerDes Serializer
TP6 PIXCLK_M VDDP A6 B5 F6 F5 J6 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5 U20 CKREF STROBE DIRI S2 S1 DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 FIN224AC
SerDes Deserializer
U22 FIN224AC
GPIO_MODE
J6 F5 F6
S1 S2 DIRI CKP DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1
TP5 C1 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5 PIXCLK_S LCD_ENABLE_S LCD_VSYNC_S LCD_HSYNC_S LCD17_S LCD16_S LCD15_S LCD14_S LCD13_S LCD12_S LCD11_S LCD LCD10_S LCD9_S Display LCD8_S In LCD7_S LCD6_S LCD5_S LCD4_S LCD3_S LCD2_S LCD1_S LCD0_S
GN D GN D
C6 1nF
C3 .01F .01uF
C12 .01F .01uF
C11
C10
D4 E3
2.2F 2.2uF 1nF
Assumptions: 1) 18-bit Unidirectional RGB Application 2) Mode 3 Operation (10 Mhz to 20Mhz CKREF) 3) VDDP= (1.65V to 3.6V)
Figure 5. FIN224AC RGB
SerDes Serializer
TP2 REFCLK LCD_/WRITE_ENABLE_M GPIO_MODE TP1 VDDP U21 FIN224AC
SerDes Deserializer
U23 FIN224AC
A6 B5 F6 F5 J6 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5
CKREF STROBE DIRI S2 S1 DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1
J6 F5 F6
S1 S2 DIRI CKP DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1
E3 D4
GN D GN D
LCD_ENABLE_M LCD_VSYNC_M LCD_HSYNC_M LCD17_M LCD16_M LCD15_M LCD14_M LCD13_M LCD12_M LCD LCD11_M Controller LCD10_M Out LCD9_M LCD8_M LCD7_M LCD6_M LCD5_M LCD4_M LCD3_M LCD2_M LCD1_M LCD0_M
B5 A6 DIRO CKP DSO+/DSIDSO-/DSI+ CKSOCKSO+ CKSICKSI+ VDDA VDDS VDDP B6 B6 C1 D6 D5 C6 C5 E6 E5 2.8V F4 E4 D3 1.8V 2.8V 2.8V F4 E4 D3 D5 D6 E6 E5 C6 C5
STROBE CKREF DIRO
DSO-/DSI+ DSO+/DSICKSICKSI+ CKSOCKSO+ VDDA VDDS VDDP
TP3
C1 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5
LCD_/WRITE_ENABLE_S
B5 A6 DIRO CKP DSO+/DSIDSO-/DSI+ CKSOCKSO+ CKSICKSI+ VDDA VDDS VDDP B6 B6 C1 D6 D5 C6 C5 E6 E5
2.8V 2.8V 1.8V 2.8V
STROBE CKREF DIRO
GN D GN D
C5 1nF
C2 .01F .01uF
C9 .01F .01uF
C8 2.2F 2.2uF
C7 1nF
D4 E3
Assumptions: 1) 18-bit Unidirectional Controller Application 2) Mode 3 Operation (10 Mhz to 20Mhz CKREF) 3) VDDP= (1.65V to 3.6V) 4) REFCLK is a continously running clock with a frequency greater than /WRITE_ENABLE.
Figure 6. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB:
Keep all four differential wires the same length. Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna.
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5 8 www.fairchildsemi.com
E3 D4
GN D GN D
LCD_/CS_M LCD_ADDRESS_M LCD17_M LCD16_M LCD15_M LCD14_M LCD13_M LCD12_M LCD LCD11_M LCD10_M Controller LCD9_M Out LCD8_M LCD7_M LCD6_M LCD5_M LCD4_M LCD3_M LCD2_M LCD1_M LCD0_M
D5 D6 E6 E5 C6 C5 F4 E4 D3
DSO-/DSI+ DSO+/DSICKSICKSI+ CKSOCKSO+ VDDA VDDS VDDP
F4 E4 D3
LCD_/CS_S LCD_ADDRESS_S LCD17_S LCD16_S LCD15_S LCD14_S LCD13_S LCD12_S LCD11_S LCD10_S LCD9_S LCD8_S LCD7_S LCD6_S LCD5_S LCD4_S LCD3_S LCD2_S LCD1_S LCD0_S
LCD Display In
FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD Supply Voltage
Parameter
Min.
-0.5 -0.5 Continuous -65
Max.
+4.6 +4.6
Unit
V V
ALL Input/Output Voltage IOS TSTG TJ TL CTL Output Short-Circuit Duration Storage Temperature Range Maximum JunctionTemperature Lead Temperature (Soldering 4 Seconds) IEC61000-4-2 ESD Human Body Model, JESD22-A114, Serial I/O Pin Human Body Model, JESD22-A114, All Pins Charged Device Model, JESD22-C101
+150 +150 +260 15.0 8.0 2.5 2.0
C C C
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VDDA, VDDS Supply Voltage VDDP TA VDDA-PP Supply Voltage
Parameter
Min.
2.5 1.65 -30
Max.
3.3 3.60 +70 100
Unit
V V C mVPP
Operating Temperature(2.) Supply Noise Voltage
Note: 2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specification should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
DC Electrical Characteristics
Values are for over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD).
Symbol
LVCMOS I/O VIH VIL
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Input High Voltage Input Low Voltage VDDP = 3.30.30
0.65 x VDDP GND
VDDP 0.35 x VDDP V
VOH
Output High Voltage
IOH = 2.0mA
VDDP = 2.5-0.20 VDDP = 1.80.18 VDDP = 3.30.30
0.75 x VDDP
V
VOL
Output Low Voltage
IOL = 2.0mA
VDDP = 2.50.20 VDDP = 1.80.18
0.25 x VDDP
V
IIN
Input Current
VIN = 0V to 3.6V
-5.0
5.0
A
DIFFERENTIAL I/O IODH IODL IOS IOZ ITH ITL IIZ IIS VICM RTRM Output HIGH source current VOS = 1.0V Output LOW sink current Short-Circuit Output Current Disabled Output Leakage Current Differential Input Threshold High Current Differential Input Threshold Low Current Disabled Input Leakage Current Short-Circuit Input Current Input Common Mode Range CKSI, DSI = 0V to VDDS S2 = S1 = 0V VOUT = VDDS VDDS = 2.775 5% 0.5 100 VDDS-1 1 VOS = 1.0V VOUT = 0V Driver Enabled Driver Disabled CKSO, DSO = 0V to VDDS S2 = S1 = 0V 50 -50 5 1 5 5 -1.75 0.950 mA mA mA A A A A A mA V
CKSI, DS Internal Receiver VID = 50mV, VIC = 925mV, DIRI = 0 Termination Resistor | CKSI+ - CKSI- | = VID
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Power Supply Currents
Typical values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD).
Symbol
IDDA1 IDDA2 IDDS1 IDDS2 IDD_PD
Parameter
VDDA Serializer Static Supply Current VDDA Deserializer Static Supply Current VDDS Serializer Static Supply Current VDDS Deserializer Static Supply Current VDD Power-Down Supply Current IDD_PD = IDDA
Test Conditions
All DP and Control Inputs at 0V or NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or NOCKREF, S2 = 0, S1 = 1, DIR = 0 All DP and Control Inputs at 0V or NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or NOCKREF, S2 = 0, S1 = 1, DIR = 0 S1 = S2 = 0 All Inputs at GND or VDD S2 = 0 S1 = 1 5MHz
1.2MHz
Min.
Typ.
450 550 4 4.5 0.1 9 14 9 17 9 16 5 6 4 5 7 11 8 8 10 12
Max. Unit
A A mA mA A
26:1 Dynamic Serializer IDD_SER1 Power Supply Current IDD_SER1 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 1 5MHz DIRI = H S1 = 0 15MHz S2 = 1 10MHz S1 = 1 26MHz S2 = 0 2MHz S1 = 1 5MHz
mA
26:1 Dynamic Deserializer IDD_DES1 Power Supply Current IDD_DES1 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 1 5MHz S1 = 0 15MHz DIRI = L S2 = 1 10MHz S1 = 1 26MHz 2MHz NO CKREF STROBE Active CKSI = 15x STROBE DIRI = H
mA
26:1 Dynamic Serializer IDD_SER2 Power Supply Current IDD_SES2 = IDDA+IDDS+IDDP
5MHz 10MHz 15MHz
mA
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
AC Electrical Characteristics
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD).
Symbol
Parameter
Test Conditions
S2=0 S1=1
Min.
200 66 38.46 2.25 x fSTROBE 0.2 0.2
Typ.
Max.
500 200 100.00
Unit
Serializer Input Operating Conditions
tTCP CKREF Clock Period (2MHz - 26MHz) CKREF Frequency Relative to STROBE CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH/LOW Maximum Serial Data Rate DP(n) Setup to STROBE DP(n) Hold to STROBE Transmitter Clock Input to Clock Output Delay CKSO Position Relative to DS(3.) Figure 9. Figure 9. S2=0 S1=1 fMAX tSTC tHTC CKREF x 26 S2=1 S1=0 S2=1 S1=1 DIRI = 1 (Tx4)/26 52 130 260 2.5 2.0 CKREF = STROBE Figure 7. CKREF does not = STROBE S2=1 S1=0 S2=1 S1=1 fREF tCPWH tCPWL tCLKT tSPWH S2=0 S1=1 ns
MHz 0.5 0.5 90.0 (Tx22)/26 130 390 676 ns ns Mb/s T T ns ns
Serializer AC Electrical Characteristics tTCCD tSPOS CKREF = STROBE 33a+1.5 -50 35a+6.5 250 ns ps
PLL AC Electrical Characteristics tTPLLS0 tTPLLD0 tTPLLD1 Serializer Phase Lock Loop Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time
(4.)
Figure 11. Figure 12. Figure 13.
200 30 20
s s ns
Deserializer Input Operating Conditions tS_DS tH_DS Serial Port Setup Time, DS-to-CKSI(5.) Serial Port Hold Time, DS-to-CKS(5.) 1.4 -250 ns ps
Deserializer AC Electrical Characteristics tRCOP tRCOL tRCOH tPDV tROLH tROHL Deserializer Clock Output (CKP OUT) Period(6.) CKP OUT Low Time(6.) CKP OUT High Time Data Valid to CKP LOW Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) Figure 10. (Rising Edge STROBE) Serializer source STROBE = CKREF Figure 10. (Rising Edge STROBE) Figure 10. CL = 8pF Figure 7. CL = 8pF Figure 7. 50 13a-3 13a-3 8a-6 18 18 500 13a+3 13a+3 8a+1 ns ns ns ns ns ns
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Notes: 3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid. 4. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies dependent upon the operating mode of the device. 5. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI and jitter effects. 6. a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13 bit times.
Control Logic Timing Controls
Symbol
tPHL_DIR, tPLH_DIR tPLZ, tPHZ tPZL, tPZH
Parameter
Propagation Delay DIRI-to-DIRO Propagation Delay DIRI-to-DP Propagation Delay DIRI-to-DP
Test Conditions
DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW
Min. Typ. Max. Units
17 25 25 ns ns ns
tPLZ, tPHZ
DIRI = 0, Deserializer Disable Time: S1(2) = 0 and S2(1) = LOW-to-HIGH, S0 or S1 to DP Figure 14. Deserializer Enable Time: S0 or S1 to DP Serializer Disable Time: S0 or S1 to CKSO, DS Serializer Enable Time: S0 or S1 to CKSO, DS DIRI = 0,(7.) S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 14. DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 13. DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH, Figure 13.
25
ns
tPZL, tPZH
2
s
tPLZ, tPHZ
25
ns
tPZL, tPZH
65
ns
Note: 7. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
CIN CIO CIO-DIFF
Parameter
Test Conditions
Min. Typ. Max. Units
2 2 2 pF pF pF
Capacitance of Input Only Signals, DIRI = 1, S1 = S2 = 0, CKREF, STROBE, S1, S2, DIRI VDD = 2.5V Capacitance of Parallel Port Pins DP1:12 Capacitance of Differential I/O Signals DIRI = 1, S1 = S2 = 0, VDD = 2.5V DIRI = 0, S1 = S2 = 0, VDD = 2.775V
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms
Setup Time
STROBE DP[1:12] Data tSTC
tROLH DPn 20%
tROHL 80% 80% 20%
Hold Time
DPn 8pF
STROBE DP[1:12] Data
tHTC
Setup: MODE0 = "0" or "1", MODE1 = "1", SER/DES = "1"
Figure 7. LVCMOS Output Load and Transition Times
Figure 8. Serial Setup and Hold Times
Data Time
tCLKT 90% 90% tCLKT
CKP DP[1:12]
tPDV
Data
10% tTCP CKREF 50% VIH VIL tCPWH tCPWL
10%
tRCOP 50% 75% 50% 25% tRCOL
CKREF
50%
tRCOH
Setup: EN_DES = "1", CKSI and DSI are valid signals
Figure 9. LVCMOS Clock Parameters
Figure 10. Deserializser Data Valid Window Time and Clock Output Parameters
tTPLLS0 VDD/VDDA S1 or S2 CKREF CKS0
Note: CKREF Signal is free running.
Figure 11. Serializer PLL Lock Time
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms (Continued)
tTPPLD0 CKREF
CKS0 Note: CKREF Signal can be stopped either High or LOW
Figure 12. PLL Loss of Clock Disable Time
tPLZ(HZ) S1 or S2
tPZL(ZH)
tTPPLD1
S1 or S2 CKS0
DS+,CKS0+ DS+,CKS0HIGHZ
Note: CKREF must be active and PLL must be stable
Figure 13. PLL Power-Down Time
Figure 14. Serializer Enable and Disable Time
tPLZ(HZ) S1 or S2
tPZL(ZH)
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 15. Deserializer Enable and Disable Times
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Tape and Reel Specification
MLP Embossed Tape Dimension
Dimensions are in millimeters.
T P0 D P2 E F K0 Wc B0 W
Tc A0 P1 D1 User Direction of Feed
Package 5x5
A0 0.1 5.35
B0 0.1 5.35
D 0.05 1.55
D1 Min. 1.50
E 0.1 1.75
F 0.1 5.50
K0 0.1 1.40
P1 Typ. 8.00
P0 Typ. 4.00
P2 0/05 2.00
T Typ. 0.30
TC 0.005 0.07
W 0.3
WC Typ.
12.00 9.30
6x6 6.30 6.30 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30 Notes: Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters.
10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View)
1.0mm maximum 1.0mm maximum Sketch C (Top View)
B0
10 maximum component rotation Sketch A (Side or Front Sectional View)
Component Rotation
Component lateral movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min Dia C Dia D min
Dia A max
Dia N
DETAIL AA See detail AA
W3
Tape Width 8 12 16
Dia A Max. 330.0 330.0 330.0
Dim B Min. 1.5 1.5 1.5
Dia C +0.5/-0.2 13.0 13.0 13.0
Dia D Min. 20.2 20.2 20.2
Dim N Min. 178.0 178.0 178.0
Dim W1 +2.0/-0 8.4 12.4 16.4
Dim W2 Max. 14.4 18.4 22.4
Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions
0.15 C
6.00
B A
(0.80) 6.00
PIN #1 IDENT 6.38MIN 0.15 C 4.77MIN 4.37MAX
0.80 MAX 0.10 C (0.20) 0.20MIN X4
0.08 C
0.05 0.00
C
SEATING PLANE
0.28 MAX 4.20 4.00 X40 0.50 0.30
0.50TYP
E
0.50 4.20 4.00 PIN #1 ID
(DATUM B)
(DATUM A)
0.18-0.30
0.50
0.10 0.05
CAB C
NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION.. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP40Arev3.
Figure 16. 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO0220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions (Continued)
2X
0.10 C
3.50
2X
0.10 C
(0.35) (0.6) 2.5
(0.5) (0.75)
TERMINAL A1 CORNER INDEX AREA
4.50 0.5
3.0
0.5 O0.30.05
BOTTOM VIEW
X42
0.15 0.05 CAB C
(QA CONTROL VALUE)
0.890.082 0.450.05 0.210.04
1.00 MAX
0.10 C
C
SEATING PLANE
0.08 C
0.230.05
0.2+0.1 -0.0
LAND PATTERN RECOMMENDATION
Figure 17. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Note: Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/packaging/bga42.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
18
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FIN224AC -- 22-Bit Bi-Directional Serializer/Deserializer
(c) 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5
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